The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a vertical-type non-volatile memory device.
A non-volatile memory device maintains data stored therein although a power source is cut off. As the industry approaches a limitation in improving the integration degree of a two-dimensional memory device, which is fabricated in a single layer over a silicon substrate, a technology of fabricating a non-volatile memory device of a three-dimensional structure by depositing memory cells vertically from a silicon substrate is suggested to overcome the limitation.
Hereafter, a conventional method of fabricating a non-volatile memory device having a three-dimensional structure and problems thereof will be described in detail.
FIGS. 1A to 1D are perspective views illustrating a conventional vertical-type non-volatile memory device.
Referring to FIG. 1A, interlayer dielectric layers 11 and a conductive layer 12 for a gate electrode are alternately formed to form a lower selection transistor (LST) over a substrate 10 with a source region S, and the interlayer dielectric layers 11 and the conductive layer 12 for a gate electrode are etched to expose the source region S.
Subsequently, a gate insulation layer (not shown) is formed on the internal walls of trenches for channels. The trenches for channels are filled with a material layer for channels to thereby form channels CH. Through this process, the LST is fabricated.
Subsequently, over the substrate with the LST formed thereon, a plurality of interlayer dielectric layers 13 and a plurality of conductive layers 14 for a gate electrode are alternately formed to form a plurality of memory cells MC.
Subsequently, the interlayer dielectric layers 13 and the conductive layers 14 for a gate electrode are etched to form trenches for channels that expose the channels CH of the LST. Subsequently, a charge blocking layer, a charge trapping layer, and a tunnel insulation layer (not shown) are formed on the internal walls of the trenches for channels, and then channels CH of memory cells MC integrated with the channels CH of the LST are formed. As a result, a plurality of memory cells MC stacking along the channels CH are formed.
Referring to FIG. 1B, the interlayer dielectric layers 11 and 13 and the conductive layers 12 and 14 for gate electrodes with the LST and the memory cells MC are etched to thereby separate a plurality of memory blocks one from another.
In the drawing, the interlayer dielectric layers etched during the memory block separation process are denoted with reference numerals 11A and 13A, while the conductive layers for gate electrodes etched during the memory block separation process are denoted with reference numerals 12A and 14A.
Referring to FIG. 1C, the etched interlayer dielectric layers 11A and 13A and the etched conductive layers 12A and 14A for gate electrodes of the memory blocks MB are patterned in step-index to expose the surface of each etched conductive layer 12A or 14A for a gate electrode. In the drawing, the plurality of the interlayer dielectric layers patterned in step-index are denoted with reference numerals 11B and 13B, and the conductive layers for gate electrodes patterned in step-index are denoted with reference numerals 12B and 14B.
The process of patterning the plurality of the interlayer dielectric layers 11B and 13B and the conductive layers 12B and 14B for gate electrodes is referred to as a slimming process. The slimming process is performed to expose the surface of the plurality of the patterned conductive layers 12B and 14B for gate electrodes to form contact plugs connected to the surface of the plurality of the patterned conductive layers 12B and 14B for gate electrodes in a subsequent process.
According to the slimming process, an etch process is performed using photoresist patterns that expose the regions reserved for contact plugs, while covering memory cell regions to function as etch barriers. The etch process is repeatedly performed while gradually decreasing the width of the photoresist patterns. Through the process, the plurality of the patterned interlayer dielectric layers 11B and 13B and the patterned conductive layers 12B and 14B for gate electrodes are patterned in step-index.
Herein, the width of the first photoresist pattern conductive layer for a gate electrode is formed to have a width as wide as to expose the regions for contact plugs of the lowermost conductive layer 12B for a gate electrode while covering all memory cell regions stacked over the substrate. The etch process is repeatedly performed under the same conditions while decreasing the width of the photoresist patterns as much as the width of the regions for contact plugs. Since the etch process is performed repeatedly while maintaining the etch step height among the plurality of the stacked memory cells, both sidewalls of the memory blocks MB are patterned in step-index.
Through the slimming process, the patterned conductive layers 12B and 14B for gate electrodes are exposed in each layer.
Referring to FIG. 1D, a conductive layer 16 for a gate electrode and an interlayer dielectric layer 15 are formed over the plurality of the memory blocks patterned in step-index in order to form an upper selection transistor (UST). Then, the interlayer dielectric layer 15 and the conductive layer 16 for a gate electrode are etched to form trenches for channels that expose the channels CH of the memory cells MC.
Subsequently, after a gate insulation layer (not shown) is formed on the internal walls of the trenches for channels, the trenches are filled with a layer for channels to thereby form channels CH of the UST integrated with the channels CH of the memory cells MC. Through this process, the UST is formed.
As a result of the processes, a string is formed of a plurality of memory cells MC connected in series between the LST and the UST. In other words, the string is arrayed vertically with respect to the substrate 10.
The conventional technology described above, however, may have a problem while the trenches for channels are formed because the LST, the memory cells MC and the UST are sequentially formed. Hereafter, problems that may occur during the fabrication of a conventional vertical channel type non-volatile memory device will be described in detail with reference to the accompanying drawings.
FIGS. 2A to 2C are cross-sectional views illustrating a process for fabricating a conventional vertical channel type non-volatile memory device. For the sake of convenience in description, the focus of illustration will be put on the process of forming a plurality of memory cells and the UST, and the other processes and some layers are omitted.
Referring to FIG. 2A, a plurality of interlayer dielectric layers 21 and a conductive layer 22 for a gate electrode are formed over a substrate 20 and the LST is formed through a predetermined process. Herein, since the method for forming the LST is the same as the method described with reference to FIG. 1A, the description will be omitted herein.
Subsequently, a plurality of interlayer dielectric layers 23 and a plurality of conductive layers 24 for gate electrodes are alternately formed to form a plurality of memory cells MC over the substrate with the LST formed thereon. The interlayer dielectric layers 23 and the conductive layers 24 for gate electrodes are etched to thereby form trenches that expose channels CH of the LST.
Herein, over-etch is performed to sufficiently expose the channels CH of the LST. During the over-etch, the surface of the channels CH of the LST is etched in a predetermined thickness. Subsequently, a material layer 25 for channels is formed over the substrate with the trenches formed therein.
Referring to FIG. 2B, a planarization process is performed until the surface of the uppermost interlayer dielectric layer 23 is exposed. By doing so, channels CH of the plurality of the memory cells MC connected to the channels CH of the LST are formed, and the plurality of the memory cells MC are formed to be stacked along the channels (CH) protruded from the substrate 20.
However, the uppermost interlayer dielectric layer 23 is partially etched during the planarization process. In the drawing, the uppermost interlayer dielectric layer damaged during the planarization process is denoted with reference numeral 23A.
Referring to FIG. 2C, a slimming process is performed onto the substrate with the LST and the plurality of the memory cells MC formed thereon. In the drawing, the plurality of the interlayer dielectric layers obtained after the slimming process are denoted with reference numerals 21A and 23A, and the conductive layers for gate electrodes obtained after the slimming process are denoted with reference numerals 22A and 24A. Also, the uppermost interlayer dielectric layer damaged during the planarization process is denoted with reference numeral 23B.
Subsequently, a plurality of interlayer dielectric layers 26 and a conductive layer 27 for a gate electrode are formed to form a UST over the substrate obtained after the slimming process.
Subsequently, trenches for exposing the surface of the channels of the memory cells MC are formed by etching the plurality of the interlayer dielectric layers 26 and the conductive layer 27 for a gate electrode. Herein, over-etch is performed to sufficiently expose the channels CH of the memory cells MC, and the channels CH of the memory cells MC are etched by a predetermined thickness as well during the over-etch.
Since overlay margins become insufficient as the integration degree of a memory device increases, mask patterns used for the formation of trenches may be misaligned with regions where the trenches are to be formed.
In other words, although the trenches for channels of the UST have to be formed at regions aligned with the channels CH of the memory cells MC formed in the lower part, the lack of overlay margins may cause the trenches for channels of the UST to be misaligned with the channels CH of the memory cells MC. Therefore, there is a problem in that the conductive layer 24A for a gate electrode of the memory cells MC formed in the lower part is exposed.
Subsequently, the channels CH of the UST are formed by forming a material layer for channels over the substrate with the trenches formed therein, and performing a planarization process until the surface of the uppermost interlayer dielectric layer 26 is exposed.
However, when the conductive layer 24A for a gate electrode of the memory cells MC is exposed by the misalignment during the formation of the trenches for channels of the UST, the channel CH of the UST contacts (see region 1 of FIG. 2C) the conductive layer 24A for a gate electrode of the memory cells MC. As a result of this contact, a short-induced defect may occur.
In this specification, problems occurring when the UST is formed after a plurality of memory cells MC are formed have been described. However, such problems may also occur when a plurality of memory cells MC are formed after the LST is formed.
Also, although the present specification describes problems occurring when memory cells MC are formed by stacking a plurality of interlayer dielectric layers and a conductive layer for a gate electrode over a substrate, the same problems may occur in the middle of a process for fabricating a vertical channel type non-volatile memory device by sequentially forming an LST, a plurality of memory cells MC, and the UST.
For example, the same problems may occur in a process of fabricating a vertical-type non-volatile memory device including a plurality of memory cells stacked along channels by stacking a plurality of interlayer dielectric layer and a sacrificial layer over a substrate to thereby form the channels and selectively removing the sacrificial layer to thereby sequentially form a tunnel insulation layer, a charge trapping layer, a charge blocking layer, and a conductive layer for a gate electrode in a region from which the sacrificial layer is removed.
Meanwhile, when trenches for channels are formed, a plurality of trenches are formed by one-time etch. However, although the etch process is performed simultaneously under the same conditions, the etch depth becomes different according to a region where a trench is to be formed, a pattern density of the surrounding area and the like. This is called a loading effect. In short, some of the plurality of the trenches may be under-etched lower than a target depth and some others may be over-etched.
For instance, when trenches for channels of the UST are formed, over-etch is performed to sufficiently expose the channels CH of the memory cells MC. Herein, over-etch is performed in consideration of the loading effect so that all trenches are etched more than a target depth, that is, the channels CH of the memory cells MC could be sufficiently etched. Therefore, the probability that the conductive layer for a gate electrode of the memory cells MC is exposed increases.